The present disclosure relates to a semiconductor device and a method of operation. More specifically, the disclosure relates to a transistor comprising transistor cells with different threshold voltages.
Power metal oxide semiconductor field effect transistors (MOSFETs) are typically used as electronically controlled power switches. Depending on the application, for example in linear regulators or electronic loads, these power MOSFETs are operated in the linear region (i.e. linear mode). When operating in the linear region, power MOSFET devices experience high thermal stress during switching instances, where the drain current and drain-source voltage are simultaneously high resulting in high power being dissipated by the devices.
Modern power MOSFET devices with small cell pitches (<10 μm), that is the distance between adjacent transistor cells on the device, are susceptible to thermal runaway when operated in the linear region. Small cell pitch power MOSFETs are characterised by a critical current density JC above which an operating current density in the device decreases with increasing temperature, but below which the operating current density in the device increases with increasing temperature. If a power MOSFET is operated below the critical current density JC, a small increase in temperature increases the operating current density. This effect causes an increase in device temperature, which in turn causes still higher current density, eventually leading to thermal runaway.
The critical current density JC of a device is governed by two competing effects. Firstly, in operation, the channel resistance of the MOSFET device increases due to heating in the device which may lead to a reduction in the current density. Secondly, the threshold voltage of the power MOSFET may reduce with increasing temperature. When operating in the linear region, the decreased threshold voltage in the device alters the effective gate voltage, thereby increasing the operating current density of the device with increasing temperature. As the gain increases, the second effect becomes more important. Modern power MOSFETS with small cell pitches have high values of gate width per unit area and are operated at currents such that the second effect is dominant, that is, the MOSFETs are operated below the critical current density JC. The consequence of this is that these MOSFETs are more prone to thermal runaway which can lead to device failure.
There is accordingly a need for a MOSFET in which one or more of the problems are alleviated.
For example in automotive applications, FETs can be optimised for energy efficiency such that they have low on resistance (Rdson), but at the same time are able to withstand high voltage surges or transients caused by unexpected load dump scenarios. A load dump occurs when a connection to an automobile battery suddenly fails in a motor vehicle and the charging current provided by a vehicle generator continues to flow for a period of time. This current has to be absorbed or taken up by the automobile electronics until the vehicle alternator is turned off. Typically, in such applications, FETs are not operated in the linear region.
Such FETs consist of providing semiconductor regions, where each region has a channel width w and the channel length l, and the ratio of the channel width to length is larger for one region than the other. Each region is electrically linked to a gate terminal via different predetermined resistors.
Such devices are formed of intermeshed FETs in parallel distributed by two gate bus-bars and interconnected by a network of resistors and diodes. The diode circuitry is placed between the gate and drain of the FETs. Such a configuration may help improve energy handling during for example clamped inductive handling, particularly during load dump scenarios. Therefore these utilise intermeshed FETs with the same threshold voltage.
In some applications, FETs may also be optimised for reduced parasitic capacitance. For example, stripe trench FETs can be configured with a number of transistor cells having varying voltage thresholds. By dividing some of the cells into a plurality of regions with varying threshold voltages, when the transistor is first turned on, conduction will occur preferentially in regions of low threshold voltage. The current density in these regions will accordingly be higher, either above the critical current density JC or just below it, reducing risk of thermal runaway.
These cells are arranged as stripes to have varying threshold voltage regions distributed along at least some of the stripes in order to mitigate increased current density. By ensuring that lower threshold voltage regions are distributed along the same stripes as the higher threshold voltage regions, large areas of high current can be avoided thus reducing the risk of current crowding that can lead to thermal runaway in the device.
When used in switching applications, a voltage clamp circuit may be connected to these FETs to ensure that voltage spikes or transients on the voltage rails do not cause damage to the device during turn-off. A dual threshold voltage approach may be adopted, with a large number of high threshold voltage cells and a small number of low threshold voltage cells. In linear mode operation, the low threshold voltage cells are turned on in these devices. This allows the current density in these regions of the device to increase, either above the critical current density Jc or less far below it.